ACEN Semiconductor

Team work

ASIC/FPGA Design Solutions

The ACEN design team holds wide experience in rapid prototyping and system development on FPGA and CPLD based platform. Besides the strong background to developing proprietary algorithm in several niches (security, cryptography, biometric identification, image analyzes), the R&D team adopts state-of-art FPGA devices from several market leaders (Altera, Xilinx, Lattice). With these policy, ACEN's design productivity are greatly improved to meet rigorous time-to-market and performance barrier with cost-effective solution. On purpose to ensuring that complex design achieves closure in area, functionality, timing and power, advanced OVM/TLM methodology is adopted in ASIC flow to handle tough and tedious functional verification task. Verification team develops complete verification document that described overall strategy, architecture and implementation approach that would be taken to build the verification infrastructure. As long-term strategy, our R&D team works closely with world-leading semiconductor foundry and keeps collaborative relationships with universities, research center, fabless company, IP provider and EDA leading-edge vendors.

The ASIC/FPGA service includes follower topics

Requirement Engineering
SPEC to Sign-Off
SPEC model development (Electronic System Level Modeling)
SPEC to Algorithm/RTL Design
SPEC to FPGA Prototyping
RTL to GDSII ( Hard/Soft IP Core Development )
Verification IP/Service(OVM/TLM)
FPGA to ASIC Migration
GDSII to Tape-Out ( Foundry MPW Program )
DFT Insertion ( Memory BIST, JTAG, DFT, and ATPG Service )
Sign Off to Tape-Out
ECO service
Third part IP Customization and Integration
IP Resale/Consulting/Qualification
Pos-Manufacturing Test and Bonding Service (Partners)